int eth32_set_pwm_duty_period(eth32 handle, int channel, int period);
This function sets the duty period for a PWM channel, which is the length of time the PWM output is active during each PWM cycle. The duty period is specified as PWM clock counts less one. In other words, when the PWM channel state is in normal mode, the PWM output will be high for (period + 1) counts of the PWM clock and low for the remainder of the clock counts in the cycle. The length of the PWM cycle is called the base period and set using the eth32_set_pwm_base_period function.
handle - The value returned by the eth32_open function.
channel - Specifies the PWM channel number (0 or 1).
period - Specifies the duty period for the channel, in terms of PWM clock counts (0-65535).
This function returns zero on success and a negative error code on failure. Please see the Error Codes section for possible error codes.
Remember that the base period (set with eth32_set_pwm_base_period) is shared between both PWM channels on the device. However, the duty period (set with this function) is individually configurable for each channel. The recommended approach is to choose a PWM frequency that is appropriate for both channels and set the base period accordingly once during initialization. After that point, the individual duty periods for each channel should be set whenever necessary in order to alter the percentage of time the channel is on (duty cycle).
Any 16-bit value can be specified for the period, from 0 to 65535. Note that if a duty period is given that is greater than or equal to the current PWM base period, the output will be a solid high (in normal mode) or a solid low (in inverted mode). If a duty period of 0 is given, the output will not be solid, but rather it will have a short spike during each period of the PWM clock.
// Error handling is omitted for clarity eth32 handle; // .... Your code that establishes a connection here // Set up PWM channel 0 to have a 10 KHZ, 60% PWM signal: // First, set up the base period to give a frequency of 10 KHZ // This is calculated as: // (2,000,000)/(10,000) - 1 // We subtracted one since the base period takes one clock // cycle longer than the value we load in. eth32_set_pwm_base_period(handle, 199); // Set up this PWM channel's duty period to take up 60% of // each base period cycle. The base period takes 200 clock // cycles, so we want the duty period to take: // 200 * 0.60 = 120 clock cycles // Since the duty period takes one cycle longer than the value // we load into it, we specify 119 here: eth32_set_pwm_duty_period(handle, 0, 119); // Put the PWM pin into output mode // PWM 0's output pin is on Port 2, bit 4 eth32_set_direction_bit(handle, 2, 4, 1); // Enable the main PWM clock eth32_set_pwm_clock_state(handle, PWM_CLOCK_ENABLED); // Finally, enable the PWM channel eth32_set_pwm_channel(handle, 0, PWM_CHANNEL_NORMAL);